Courses Offered

Physical Design (PD)

Master industry-level Physical Design skills — from RTL to GDSII — through practical, hands-on experience with live projects and expert guidance.

🎓 Overview

This course is designed to give you end-to-end exposure to the Physical Design flow used in the semiconductor industry. You’ll learn by executing real-world projects using industry-standard EDA tools, covering all major stages from Floor planning to Signoff closure.

✅ Eligibility

 B.Tech/Diploma students in EEE, ECE, or EIE (pursuing or completed).
 M.E/M.Tech/M.S students in VLSI, Embedded Systems, or related fields.
 Working professionals seeking to upskill in VLSI design.
 Anyone passionate and curious about chip design.

💻 Mode of Study

 Online Mode – Learn from anywhere with live interactive sessions.
 Offline Mode – Coming Soon.

🎯 Learning Outcomes

By the ends of this course, you will:

 Gain deep practical knowledge in Physical Design concepts and EDA tools.
 Learn how to implement PnR. floor planning, power planning, placement, clock tree synthesis & routing.
 Execute industry-grade RTL-to-GDSII projects.
 Develop the expertise required for VLSI job interviews and professional roles.

🔑 Key Course Features

 Job assistance and tool support.
 Hands-on industry live projects guided by trainers with 8+ years of experience.
 Comprehensive course material, handouts, quizzes, and assignments.
 Updated content based on latest industry practices and interview trends.

🕒 Course Details

 Duration: 6 - 8 Months.
 Skill Level: Intermediate.
 Language: English/Hindi.
 Assessments: Included.

📖 Foundations

 Basics of MOSFET, BJT & Diode.
 Digital Electronics.
 Combinational & Sequential Circuits.
 CMOS.

⚙️ Core Physical Design Topics

 RTL to Synthesis.
 SDC & Library Details.
 Floor Planning & Power Planning.
 Placement & Routing Concepts.
 Design Optimization Techniques.
 Timing Closure and ECO Fixes.

Advanced Design Concepts

 Clock Tree Synthesis (CTS) & Clock Latency Calculations.
 Buffer Tree Synthesis.
 Latch-up and Antenna Effects.
 Fence, Region, Padding, Blockages, Bump, Don’t Touch, Filter Gap, DRV Optimization.

⚡ Extra (Advanced Topics)

 Physical Verification (ERC, LVS, & DRC Details and Fixes),
 Cross Talk,
 EMIR Analysis,
 Static & Dynamic IR Drop Analysis,
 PG EM, Signal EM, and Inrush Analysis,
 TCL Fundamentals, TCL Programming.

Outcome:

Become ready for Physical Design Engineer roles in semiconductor companies.

Static Timing Analysis (STA)

Think of a relay race—each runner must pass the baton at the right time. If someone is too slow or too early, the entire team fails.
In chip design, STA (Static Timing Analysis) acts like the timing referee. It ensures every signal (data) moves correctly from one flip-flop to the next:
 Not too late → Avoid Setup Violation
 Not too early → Avoid Hold Violation

Why Do We Need STA?

✅ Ensures the chip works correctly at its target frequency.
✅ Detects timing problems without slow gate-level simulations.
✅ Helps improve logic placement for better performance.
✅ Prevents expensive chip re-spins after fabrication.

*STA ensures that your chip behaves reliably in real hardware, chip doesn't fail when power is ON.
For every VLSI Engineer:
“Understanding STA is not optional…It's the heart of making high-performance and reliable chips.”

✅ Eligibility

 B. Tech students in EEE, ECE, or EIE (pursuing or completed).
 M.E/M.Tech students in VLSI, Embedded Systems, or related fields.
 Working professionals seeking to upskill in VLSI design.
 Anyone passionate and curious about chip design.

💻 Mode of Study [e-Learning]

 Online Mode Learn from anywhere with live in interactive sessions.

🕒 Course Details

 Duration: 6-8 Months.
 Skill Level: Intermediate.
 Language: English/Hindi.
 Assessments: Included.

Outcome:

Gain expertise to handle timing signoff and timing closure in live chip design projects.

Short Term Internship

This internship is designed to give students industry-ready exposure to the VLSI Physical Design Flow.
By the end of the program, students will understand how a real chip is designed, optimized, and prepared for fabrication.

Duration: 4 Weeks (Summer / Winter Batch)
Domain: Physical Design (RTL to GDS-II)
Mode: Online / Hybrid/Weekend
Eligibility: B.Tech / M.Tech (ECE, EE, EEE, CSE-VLSI)
Tools Exposure: Cadence / Synopsys

📜 Certification

Every participant will receive:

 Internship Completion Certificate.
 Project Report Certificate.
 Resume Building for VLSI Roles.
 Company Interview Question Practice.
 PD & STA Technical Mock Interviews.

EMIR / PDN

 EMIR analysis = Electromigration + IR Drop analysis → Used to ensure power integrity and long-term chip reliability.
 The Power Delivery Network in a chip is the complete wiring system that delivers power (VDD) and ground (VSS) to every cell, macro, and block in the design.

It ensures that:
 Each transistor receives correct supply voltage
 Power delivery is stable across chip
 Variations in power do not disturb timing or logic state

Details: Coming Soon........